- Malleableware Specification -

Diagram of a Task Unit, the basic building block of a MW chip

The design for a general purpose AI that I have spent the past few months developing incorporates a number of revolutionary (I think :) concepts. Unfortunately most of these concepts are unworkable without copious processor resources. In order to facilitate the implementation of my AI design, I have designed a new processor architecture/computing paradigm. I’ve called it Malleableware, since it straddles the definition of hardware and software.

This new architecture, its most basic component pictured to the left, relies entirely on existing technology. In addition it solves some current problems that the technology industry is dealing with.

In order to satisfy the AI’s massive processing power requirements, I decided that the raw speed and power of dedicated hardware processing was required. For the most demanding components of the (highly modular) AI design, literally every branch point, constant, memory space, etc. of the software would be on die. In essence, the source code would be compiled directly to a VLSI design diagram. At the same time, being modular in nature, the AI requires a great deal of flexibility in its configuration. This is especially important since one of the goals of my design is that the AI will eventually be able to upgrade and redesign itself. Thus the idea of malleableware was born…

The basic architectural unit of a malleableware chip is the Task Unit. As it’s name implies, it is a dedicated circuit that is capable of performing all the functions and operations of a given basic task. For example, all of the code that makes up a single Photoshop filter might be translated into the dedicated circuit portion of a single Task Unit.

Each Task Unit consists of several components, pictured to the left. These are: the dedicated circuit, an FPGA, on-die SDRAM, inter-unit data paths, and data paths connecting to other Task Units and off-chip components. The dedicated circuit (DC) and the FPGA are linked by a two-way data path, which runs at the chip’s clock frequency. In the AI design, the FPGA has processing power equivalent to perhaps ¼ of its DC counterpart. Both the DC and FPGA make use of on-die SDRAM in their functioning. DC, FPGA, and SDRAM all have 2 way data paths to other Task Units and off-chip components. At the minimum, there is 1 inter-chip input path and 1 inter-chip output path.

Each inter-chip path is connected to a logic unit, which controls where the inter-chip data will be sent. This way, input can be sent to either or both processing components of a Task Unit, and output can be directed to multiple Task Units and/or off-chip data paths. Each logic unit can delay the data for an arbitrary length of time, facilitating coordination of multi-Task Unit operations. The FPGA, with it’s off-chip and inter-chip data paths, allows modification of the Task Unit’s functionality, although this does carry a speed penalty unless the chip is designed so that the FPGA’s match the power of their DC counterparts.

Each MW chip is composed of an arbitrary number of interconnected Task Units, as well as chip-level I/O, Auxiliary DC’s, Task Unit interconnects, etc. Typically a single MW chip would equate to a single software application, such as Photoshop or MS Word. These chips would greatly stymie software piracy (Adobe PS in MW form would probably perform at least 50 times the performance of it’s software equivalent, making pirates either a) settle for a much slower version or b) replicate the chip, which could only be done on an industrial scale and would therefore be rather vulnerable to law enforcement efforts) and would be cheap to manufacture due to economics of scale. There are many, many other aspects of MW that will greatly benefit the hardware and software industries, but ideas for potential applications and products are not the scope of this document. A freely available document detailing such products and applications will be released soon, but it is not a high priority. I’m sure whoever’s reading this can think of some creative uses themselves…)

In the context of my AI, each MW chip would carry out a task equivalent to a single subroutine of a given module if said module were software based.

The MW paradigm necessitates sweeping changes in PC architecture if MW is to become widely accepted. A MW based system would still have a CPU, GPU, Mass storage, RAM, etc. The motherboard would be rather different. It would essentially form the physical layer of a very high speed/bandwidth TCP/IP mesh network. MW chips would be connected to secondary boards, each of which would hold an arbitrary number of similar purpose MW chips. Each secondary board, CPU, RAM unit, etc. would be a node on the mesh network. All internal data transfer would be in TCP/IP. In the AI, all data (and instructions) will be constructions and expressions of the Internal Symbolic Language (ISL) I have created. A preliminary specification for ISL will be released as soon as possible.

This document is only an outline; more detailed descriptions of MW components and concepts will be forthcoming.

c) 2002 Jonathan B. Standley